Cost-aware Topology Customization of Mesh-based Networks-on-Chip
Authors
Abstract:
Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based on grid-like topologies which are also used in application-specific design.The small world network idea recently has been introduced in order to optimize the performance of the Networks-on-chip. Based on this method the architecture will be neither fully customized nor completely regular. Results have shown that by using the long-range links which optimized the network power and performance, the area consumption will exceed. We can derive from this that an acceptable bound on the area consumption should be considered. Based on the restriction of a designer, in this paper we want to present a methodology that will automatically optimize an architecture while at the same time considering the area consumption.
similar resources
CAFT: Cost-aware and Fault-tolerant routing algorithm in 2D mesh Network-on-Chip
By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tol...
full textShufle-Exchange Mesh Topology for Networks-on-Chip
Network-on-Chip (NoC) is a promising communication paradigm for multiprocessor system-on-chips. This communication paradigm has been inspired from the packet-based communication networks and aims at overcoming the performance and scalability problems of the shared buses in multi-core SoCs (System on Chips)(Benini & Mecheli, 2002). Although the concept of NoCs is inspired from the traditional in...
full textTriplet-based Topology for On-chip Networks
Most CMPs use on-chip network to connect cores and tend to integrate more simple cores on a single die. As the number of cores increases, on-chip network will play an important role in the performance of future CMPs. Due to the tradeoff between the performance and area constraint in on-chip network designs, we propose the use of triplet-based topology in on-chip interconnection networks and dem...
full textSphere-based topology for networks-on-chip
This paper proposes sphere-based topology for networks-on-chips. The sphere-based topology is a new structure for network-on-chips that forms in sphere shape. The proposed topology is introduced and compared with existing ones in regard of factors such as power and latency. We have compared the performances of sphere-based topology with two other common topologies namely mesh and torus. Based o...
full textInterference-Aware and Cluster Based Multicast Routing in Multi-Radio Multi-Channel Wireless Mesh Networks
Multicast routing is one of the most important services in Multi Radio Multi Channel (MRMC) Wireless Mesh Networks (WMN). Multicast routing performance in WMNs could be improved by choosing the best routes and the routes that have minimum interference to reach multicast receivers. In this paper we want to address the multicast routing problem for a given channel assignment in WMNs. The channels...
full textMy Resources
Journal title
volume 4 issue 2
pages 11- 20
publication date 2018-05-01
By following a journal you will be notified via email when a new issue of this journal is published.
Hosted on Doprax cloud platform doprax.com
copyright © 2015-2023